ICS1531 Datasheet, PDF (32/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.6 Register 05h: DPA Control
The DPA Control (Dynamic Phase Adjust Control) Register is used to select the resolution of the Dynamic
Phase Adjust circuitry, used to adjust the pixel clock on a sub-pixel basis.
Table 6-8. DPA Control Register
Bit Bit Name
Bit Definition
05:7- Reserved
05:2
05:1- DPA_Res [1-0]
05:0
Reserved.
• See Section 6.1, “Reserved Bits”.
• These bits can be programmed to ‘0’.
Dynamic Phase Adjust Resolution [1-0].
These bits select the resolution of (that is, the number of delay
element units) for the Dynamic Phase Adjust Offset of Reg
04:5-0.
Ac- Spec. Re-
cess Func. set
–
–
–
R/W D-DPA 0
Table 6-9 lists, for the Reg 05 bit settings:
1. The resulting (decimal) number of delay element units
• 0 = The resolution is for 16 delay element units.
• 1 = The resolution is for 32 delay element units.
• 2 = Reserved.
• 3 = The resolution is for 64 delay element units.
2. The corresponding maximum values for Reg 04 DPA offset
3. The corresponding pixel clock output frequency ranges.
Important: (ICS does not recommend using the DPA above
260 MHz.)
Table 6-9. DPA Control
Reg 05:1-0
Bit 1 Bit 0
0
0
0
1
1
0
1
1
(1) Number of Delay
Element Units
(Decimal)
16
32
Reserved
64
(2) Reg 04:5-0
Max. Value
(Hex)
0F
1F
Reserved
3F
14
(3) Pixel Clock Range
(MHz)
55
27
260
130
64
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
32
December, 1999