MC68HC912BL16 Datasheet, PDF (92/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
RWU — Receiver Wake-Up Control
0 = Normal SCI Receiver
1 = Enables the wake-up function and inhibits further receiver interrupts. Normally hardware wakes
the receiver by automatically clearing this bit.
SBK — Send Break
0 = Break generator off
1 = Generate a break code (at least 10 or 11 contiguous zeros)
As long as SBK remains set the transmitter will send zeros. When SBK is changed to zero, the current
frame of all zeros is finished before the TxD line goes to the idle state. If SBK is toggled on and off, the
transmitter will send 10 (or 11) zeros and then revert to mark idle or sending data.
SC0SR1 — SCI Status Register 1
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Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
RESET:
1
1
0
0
0
0
0
0
The bits in these registers are set by various conditions in the SCI hardware and are automatically
cleared by special acknowledge sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE, OR,
NF, FE, and PF) are all cleared by a read of the SC0SR1 register followed by a read of the transmit/
receive data register L. However, only those bits which were set when SC0SR1 was read will be cleared
by the subsequent read of the transmit/receive data register L. The transmit related bits in SC0SR1
(TDRE and TC) are cleared by a read of the SC0SR1 register followed by a write to the transmit/receive
data register L.
Read anytime (used in auto clearing mechanism). Write has no meaning or effect.
TDRE — Transmit Data Register Empty Flag
New data will not be transmitted unless SC0SR1 is read before writing to the transmit data register. Re-
set sets this bit.
0 = SC0DR busy
1 = Any byte in the transmit data register is transferred to the serial shift register so new data may
now be written to the transmit data register.
TC — Transmit Complete Flag
Flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear by
reading SC0SR1 with TC set and then writing to SC0DR.
0 = Transmitter busy
1 = Transmitter is idle
RDRF — Receive Data Register Full Flag
Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF
is set if a received character is ready to be read from SC0DR. Clear the RDRF flag by reading SC0SR1
with RDRF set and then reading SC0DR.
0 = SC0DR empty
1 = SC0DR full
IDLE — Idle Line Detected Flag
Receiver idle line is detected (the receipt of a minimum of 10/11 consecutive ones). This bit will not be
set by the idle line condition when the RWU bit is set. Once cleared, IDLE will not be set again until after
RDRF has been set (after the line has been active and becomes idle again).
0 = RxD line is idle
1 = RxD line is active
OR — Overrun Error Flag
New byte is ready to be transferred from the receive shift register to the receive data register and the
receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared.
0 = No overrun
1 = Overrun detected
MC68HC912BL16
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