MC68HC912BL16 Datasheet, PDF (61/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
RTIFLG — Real-Time Interrupt Flag Register
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Bit 7
6
5
4
3
2
1
Bit 0
RTIF
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
RTIF — Real-Time Interrupt Flag
This bit is cleared automatically by a write to this register with this bit set.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
COPCTL — COP Control Register
Bit 7
6
5
4
3
2
1
CME
FCME
FCM
FCOP
DISR
CR2
CR1
RESET:
0
0
0
0
0
0
0
RESET:
0
0
0
0
1
0
0
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Bit 0
CR0
1
Normal
1
Special
CME — Clock Monitor Enable
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
0 = Clock monitor is disabled. Slow clocks and stop instruction may be used.
1 = Slow or stopped clocks (including the stop instruction) will cause a clock reset sequence.
FCME — Force Clock Monitor Enable
Write once in normal modes, anytime in special modes. Read anytime.
In normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence.
In order to use both STOP and clock monitor, the CME bit should be cleared prior to executing a STOP
instruction and set after recovery from STOP. If you plan on using STOP always keep FCME = 0.
FCM — Force Clock Monitor Reset
Writes are not allowed in normal modes, anytime in special modes. Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = Force a clock monitor reset (if clock monitor is enabled).
FCOP — Force COP Watchdog Reset
Writes are not allowed in normal modes; can be written anytime in special modes. Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = Force a COP reset (if COP is enabled).
DISR — Disable Resets from COP Watchdog and Clock Monitor
Writes are not allowed in normal modes, anytime in special modes. Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor will not generate a system reset.
CR2, CR1, CR0 — COP Watchdog Timer Rate Select Bits
The COP system is driven by a constant frequency of E/2¹³. (RTBYP in the RTICTL register allows all
but two stages of this divider to be bypassed for testing in special modes only.) These bits specify an
additional division factor to arrive at the COP time-out rate (the clock used for this module is the E clock).
Write once in normal modes, anytime in special modes. Read anytime.
MC68HC912BL16TS/D
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