MC68HC912BL16 Datasheet, PDF (38/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
This register controls the operation of the Flash EEPROM array. BOOTP cannot be changed when the
LOCK control bit in the FEELCK register is set or if ENPE in the FEECTL register is set.
BOOTP — Boot Protect
The boot block is located at $7800–$7FFF or $F800–$FFFF depending upon the mapped location of
the Flash EEPROM array.
0 = Enable erase and program of 2-Kbyte boot block
1 = Disable erase and program of 2-Kbyte boot block
FEETST — Flash EEPROM Module Test Register
$00F6
Bit 7
6
5
4
3
2
1
Bit 0
FSTE GADR
HVT
FENLV FDISVFP VTCK STRE MWPR
RESET:
0
0
0
0
0
0
0
0
In normal mode, writes to FEETST control bits have no effect and always read zero. The Flash
EEPROM module cannot be placed in test mode inadvertently during normal operation.
FSTE — Stress Test Enable
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
GADR — Gate/Drain Stress Test Select
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
HVT — Stress Test High Voltage Status
0 = High voltage not present during stress test
1 = High voltage present during stress test
FENLV — Enable Low Voltage
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
FDISVFP — Disable Status V_FP Voltage Lock
When the V_FP pin is below normal programming voltage the Flash module will not allow writing to the
LAT bit; the user cannot erase or program the Flash module. The FDISVFP control bit enables writing
to the LAT bit regardless of the voltage on the V_FP pin.
0 = Enable the automatic lock mechanism if V_FP is low
1 = Disable the automatic lock mechanism if V_FP is low
VTCK — V_T Check Test Enable
When VTCK is set, the Flash EEPROM module uses the V_FP pin to control the control gate voltage; the
sense amp time-out path is disabled. This allows for indirect measurements of the bit cells program and
erase threshold. If V_FP < V_ZBRK (breakdown voltage) the control gate will equal the V_FP voltage.
If V_FP > V_ZBRK the control gate will be regulated by the following equation:
Vcontrol gate = V_ZBRK + 0.44 × (V_FP − V_ZBRK)
0 = V_T test disable
1 = V_T test enable
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains
production test information which must be maintained through several erase cycles. When STRE is set,
the decoding for the spare test row overrides the address lines which normally select the other rows in
the array.
MC68HC912BL16
38
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