MC68HC912BL16 Datasheet, PDF (118/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
Command
READ_NEXT
READ_PC
READ_D
READ_X
READ_Y
READ_SP
WRITE_NEXT
WRITE_PC
WRITE_D
WRITE_X
WRITE_Y
WRITE_SP
GO
TRACE1
TAGGO
Table 39 BDM Firmware Commands
Opcode (Hex)
62
63
64
65
66
67
42
43
44
45
46
47
08
10
18
Data
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
None
None
None
Description
X = X + 2; Read next word pointed-to by X
Read program counter
Read D accumulator
Read X index register
Read Y index register
Read stack pointer
X = X + 2; Write next word pointed-to by X
Write program counter
Write D accumulator
Write X index register
Write Y index register
Write stack pointer
Go to user program
Execute one user instruction then return to BDM
Enable tagging and go to user program
Each of the hardware and firmware BDM commands start with an 8-bit command code (opcode). De-
pending upon the commands, a 16-bit address and/or a 16-bit data word is required as indicated in the
tables by the command. All the read commands output 16-bits of data despite the byte/word implication
in the command name.
The external host should wait 150 E-clock cycles for a non-intrusive BDM command to execute before
another command is sent. This delay includes 128 E-clock cycles for the maximum delay for a free cy-
cle. For data read commands, the host must insert this delay between sending the address and attempt-
ing to read the data.( In the case of a write command, the host must delay after the data portion, before
sending a new command, to be sure the write has finished.
The external host should delay about 32 target E-clock cycles between a firmware read command and
the data portion of these commands. This allows the BDM firmware to execute the instructions needed
to get the requested data into the BDM SHIFTER register.
The external host should delay about 32 target E-clock cycles after the data portion of firmware write
commands to allow BDM firmware to complete the requested write operation before a new serial com-
mand disturbs the BDM SHIFTER register.
The external host should delay about 64 target E-clock cycles after a TRACE1 or GO command before
starting any new serial command. This delay is needed because the BDM SHIFTER register is used as
a temporary data holding register during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU12 operation.(However, if an operation
requires multiple cycles, CPU12 clocks are frozen until the operation is complete.
MC68HC912BL16
118
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