MC68HC912BL16 Datasheet, PDF (62/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
Table 21 COP Watchdog Rates (RTBYP = 0)
CR0 Divide E By:
0
OFF
1
2¹³
0
2¹⁵
1
2¹⁷
0
2¹⁹
1
2²¹
0
2²²
1
2²³
At E = 4.0 MHz
Time-Out
–0 to +2.048 ms
OFF
2.048 ms
8.1920 ms
32.768 ms
131.072 ms
524.288 ms
1.048 s
2.097 s
At E = 8.0 MHz
Time-Out
–0 to +1.024 ms
OFF
1.024 ms
4.096 ms
16.384 ms
65.536 ms
262.144 ms
524.288 ms
1.048576 s
COPRST — Arm/Reset COP Timer Register
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may
be executed between these writes but both must be completed in the correct order prior to time-out to
avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur.
SLOW — Slow mode Divider Register
$00E0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
SLDV3 SLDV2 SLDV1 SLDV0
RESET:
0
0
0
0
0
0
0
0
Read and write anytime.
The slow clock divider is included to deliver a variable clock frequency to the MCU in wait mode. This
slow clock is drived from the EXTALi and in wait mode can be used for the system clocks.
Write to this register changes the SLWCLK frequency. The frequency divide ratio is 2 times SLOW reg-
ister value, hence the divide range is 2 to 30, by steps of 2. When SLOW register = 0, the divider is
bypassed. The generation of E and P clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTAL Frequency is programmable to 2, 4, 8, 12, 16, ..., 60, by steps of 4.
Table 22 SLOW Mode Register Divider Rates
SLDV3 SLDV2 SLDV1 SLDV0
Divide By:
(SLOW * 2)
0
0
0
0
0
0
0
0
1
2
0
0
1
0
4
0
0
1
1
6
0
1
0
0
8
Bus Rate w/
16MHz XTAL
8 MHz
4 MHz
2 MHz
1.3 MHz
1 MHz
Bus Rate w/
8MHz XTAL
4 MHz
2 MHz
1 MHz
667 KHz
500 KHz
Bus Rate w/
4MHz XTAL
2 MHz
1 MHz
500 KHz
333 KHz
250 KHz
MC68HC912BL16
62
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