MC68HC912BL16 Datasheet, PDF (72/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
1 = Channel 3 is enabled.
PWEN2 — PWM Channel 2 Enable
The pulse modulated signal will be available at port P, bit 2 when its clock source begins its next cycle.
0 = Channel 2 is disabled.
1 = Channel 2 is enabled.
PWEN1 — PWM Channel 1 Enable
The pulse modulated signal will be available at port P, bit 1 when its clock source begins its next cycle.
0 = Channel 1 is disabled.
1 = Channel 1 is enabled.
PWEN0 — PWM Channel 0 Enable
The pulse modulated signal will be available at port P, bit 0 when its clock source begins its next cycle.
0 = Channel 0 is disabled.
1 = Channel 0 is enabled.
PWPRES — PWM Prescale Counter
$0043
Bit 7
6
5
4
3
2
1
Bit 0
0
Bit 6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
PWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1).
PWSCAL0 — PWM Scale Register 0
$0044
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
Read and write anytime. A write will cause the scaler counter PWSCNT0 to load the PWSCAL0 value
unless in special mode with DISCAL = 1 in the PWTST register.
PWM channels 0 and 1 can select clock S0 (scaled) as its input clock by setting the control bit PCLK0
and PCLK1 respectively. Clock S0 is generated by dividing clock A by the value in the PWSCAL0 reg-
ister plus one and dividing again by two. When PWSCAL0 = $FF, clock A is divided by 256 then divided
by two to generate clock S0.
PWSCNT0 — PWM Scale Counter 0 Value
$0045
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
PWSCNT0 is a down-counter that, upon reaching $00, loads the value of PWSCAL0. Read any time.
PWSCAL1 — PWM Scale Register 1
$0046
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
Read and write anytime. A write will cause the scaler counter PWSCNT1 to load the PWSCAL1 value
unless in special mode with DISCAL = 1 in the PWTST register.
PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by setting the control bit PCLK2
and PCLK3 respectively. Clock S1 is generated by dividing clock B by the value in the PWSCAL1 reg-
ister plus one and dividing again by two. When PWSCAL1 = $FF, clock B is divided by 256 then divided
MC68HC912BL16
72
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