MC68HC912BL16 Datasheet, PDF (78/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
12.1 Timer Registers
Input/output pins default to general-purpose I/O lines until an internal function which uses that pin is
specifically enabled. The timer overrides the state of the DDR to force the I/O state of each associated
port line when an output compare using a port line is enabled. In these cases the data direction bits will
have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing to this PORTTn bit does not
affect the pin but the data is stored in an internal latch such that if the pin becomes available for general-
purpose output the driven level will be the last value written to the PORTTn bit.
TIOS — Timer Input Capture/Output Compare Select
Bit 7
6
5
4
3
IOS7
IOS6
IOS5
IOS4
IOS3
RESET:
0
0
0
0
0
2
IOS2
0
1
IOS1
0
Bit 0
IOS0
0
$0080
Read or write anytime.
NOTE
Port T[6] is not bonded to any pin in MC68HC912BL16.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
CFORC — Timer Compare Force Register
Bit 7
6
5
4
3
2
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2
RESET:
0
0
0
0
0
0
1
FOC1
0
Bit 0
FOC0
0
$0081
Read anytime but will always return $00 (1 state is transient). Write anytime.
NOTE
Port T[6] is not bonded out to any pin in MC68HC912BL16.
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes the action which is programmed for
output compare “n” to occur immediately. The action taken is the same as if a successful comparison
had just taken place with the TCn register except the interrupt flag does not get set.
OC7M — Output Compare 7 Mask Register
$0082
Bit 7
6
5
4
3
2
1
Bit 0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
NOTE
Port T[6] is not bonded to any pin in MC68HC912BL16.
The bits of OC7M correspond bit-for-bit with the bits of timer port (PORTT). Setting the OC7Mn will set
the corresponding port to be an output port regardless of the state of the DDRTn bit when the corre-
sponding TIOSn bit is set to be an output compare. This does not change the state of the DDRT bits.
MC68HC912BL16
78
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