MC68HC912BL16 Datasheet, PDF (88/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
MCLK
BAUD RATE
CLOCK
STCRI ANSMITTER
MSB
LSB
DIVIDER
PARITY
GENERATOR
Rx Baud Rate
10-11 BIT SHIFT REG
TxD BUFFER/SC0DRL
SC0BD/SELECT
Tx Baud Rate
TxD
PS1
SC0CR1/SCI CTL 1
TxMTR CONTROL
DATA BUS
SC0CR2/SCI CTL 2
SC0SR1/INT STATUS
RxD
PS0
INT REQUEST LOGIC
TO
INTERNAL
LOGIC
PARITY
DETECT
DATA RECOVERY
SCI RECEIVER
MSB
LSB
10-11 BIT SHIFT REG
RxD BUFFER/SC0DRL
SC0CR1/SCI CTL 1
WAKE-UP LOGIC
SC0SR1/INT STATUS
SC0CR2/SCI CTL 2
INT REQUEST LOGIC
HC12B32 SCI BLOCK
Figure 22 Serial Communications Interface Block Diagram
13.2.1 Data Format
The serial data format requires the following conditions:
• An idle-line in the high state before transmission or reception of a message.
• A start bit (logic zero), transmitted or received, that indicates the start of each character.
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit, a char-
acter of eight or nine data bits and a stop bit.)
• A BREAK is defined as the transmission or reception of a logic zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
MC68HC912BL16
88
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