MC68HC912BL16 Datasheet, PDF (75/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
PWTST — PWM Special Mode Register (“Test”)
Bit 7
6
5
4
3
2
1
DISCR DISCP DISCAL
0
0
0
0
RESET:
0
0
0
0
0
0
0
$0055
Bit 0
0
0
Read anytime but write only in special mode (SMODN = 0). These bits are available only in special
mode and are reset in normal mode.
The PWM has some special test functions which are only accessible when the device is in Special
Mode. Special Mode is indicated to the PWM module when the SMOD line on the LIB is asserted.
When the SMOD line is asserted, the Special Mode register control bits are accessed via the LIB. When
SMOD is not asserted, writes to the Special Mode control bits have no effect and all bits in the Special
Mode register are forced to 0. This ensures that the PWM Special Mode can not be invoked inadvert-
ently during normal operation.
DISCR — Disable Reset of Channel Counter on Write to Channel Counter
0 = Normal operation. Write to PWM channel counter will reset channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal operation
1 = In left-aligned output mode, match of the period does not reset the associated PWM counter
register.
DISCAL — Disable Load of Scale-Counters on Write to the Associated Scale Registers
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale counters
PORTPP — Port P Data Register
Bit 7
6
5
4
3
2
1
Bit 0
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PWM
–
–
–
–
PWM3 PWM2 PWM1 PWM0
RESET:
–
–
–
–
–
–
–
–
$0056
PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when en-
abled. PORTP can be read anytime. When configured as input, a read will return the pin level. When
configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the corresponding PWM channel is
not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
NOTE
Writes do not change pin state when pin is configured for PWM outputs, only after
the PWM channel becomes available on port P pin, see PWEN bit description.
PORTPD — Port P Data Direction Register
Bit 7
6
5
4
DDP7 DDP6 DDP5 DDP4
RESET:
0
0
0
0
3
DDP3
0
2
DDP2
0
1
DDP1
0
Bit 0
DDP0
0
$0057
MC68HC912BL16TS/D
For More Information On This Product,
75
Go to: www.freescale.com