MC68HC912BL16 Datasheet, PDF (115/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
E CLOCK
(TARGET
MCU)
HOST
DRIVETO
BKGD PIN
TARGET MCU
SPEEDUP
PULSE
PERCEIVED
START OF BIT
TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 29 BDM Target to Host Serial Bit Timing (Logic 1)
EARLIEST
START OF
NEXT BIT
HC12A4 BDM TARGETTO HOSTTIM 1
Figure 29 shows the host receiving a logic one from the target MC68HC912BL16 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target E cycles). The host must release the low drive
before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start
of the bit time. The host should sample the bit level about ten cycles after it started the bit time.
E CLOCK
(TARGET MCU)
HOST
DRIVETO
BKGD PIN
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 30 BDM Target to Host Serial Bit Timing (Logic 0)
EARLIEST
START OF
NEXT BIT
HC12A4 BDM TARGETTO HOST TIM 0
Figure 30 shows the host receiving a logic zero from the target MC68HC912BL16 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
MC68HC912BL16TS/D
For More Information On This Product,
115
Go to: www.freescale.com