MC68HC912BL16 Datasheet, PDF (106/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
Table 33 ATD Response to Background Debug Enable
FRZ1 FRZ0
0
0
0
1
1
0
1
1
ATD Response
Continue conversions in active background mode
Reserved
Finish current conversion, then freeze
Freeze when BDM is active
ATDCTL4 — ATD Control Register 4
Bit 7
6
5
S10BM SMP1 SMP0
RESET:
0
0
0
4
PRS4
0
3
PRS3
0
2
PRS2
0
1
PRS1
0
Bit 0
PRS0
1
$0064
The ATD control register 4 is used to select the clock source and set up the prescaler. Writes to the ATD
control registers initiate a new conversion sequence. If a write occurs while a conversion is in progress,
the conversion is aborted and ATD activity halts until a write to ATDCTL5 occurs.
S10BM — ATD 10-bit Mode Control
0 = 8 bit operation
1 = 10 bit operation
SMP1, SMP0 — Select Sample Time
These bits are used to select one of four sample times after the buffered sample and transfer has oc-
curred. Total conversion time depends on initial sample time (fixed at two ATD clocks), transfer time
(fixed at four ATD clocks), final sample time (programmable, refer to Table 34), and resolution time
(fixed at ten ATD clocks).
Table 34 Final Sample Time Selection
SMP1
0
0
1
1
SMP0
0
1
0
1
Final Sample Time
2 ATD clock periods
4 ATD clock periods
8 ATD clock periods
16 ATD clock periods
Total 8-bit Conversion Time Total 10-bit Conversion Time
18 ATD clock periods
20 ATD clock periods
20 ATD clock periods
22 ATD clock periods
24 ATD clock periods
26 ATD clock periods
32 ATD clock periods
34 ATD clock periods
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD P-Clock Prescaler.
The binary value written to these bits (1 to 31) selects the divide-by factor for the modulo counter-based
prescaler. The P clock is divided by this value plus one and then fed into a ÷2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the output clock signal. Clearing these
bits causes the prescale value to default to one which results in a ÷2 prescale factor. This signal is then
fed into the ÷2 logic. The reset state divides the P clock by a total of four and is appropriate for nominal
operation between 2 MHz and 8 MHz bus rate. Table 35 shows the divide-by operation and the appro-
priate range of system clock frequencies.
MC68HC912BL16
106
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