MC68HC912BL16 Datasheet, PDF (63/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
Table 22 SLOW Mode Register Divider Rates
SLDV3 SLDV2 SLDV1 SLDV0
Divide By:
(SLOW * 2)
0
1
0
1
10
0
1
1
0
12
0
1
1
1
14
1
0
0
0
16
1
0
0
1
18
1
0
1
0
20
1
0
1
1
22
1
1
0
0
24
1
1
0
1
26
1
1
1
0
28
1
1
1
1
30
Bus Rate w/
16MHz XTAL
800 KHz
667 KHz
571 KHz
500 KHz
444 KHz
400 KHz
364 KHz
333 KHz
308 KHz
286 KHz
267 KHz
Bus Rate w/
8MHz XTAL
400 KHz
333 KHz
286 KHz
250 KHz
222 KHz
200 KHz
182 KHz
167 KHz
154 KHz
143 KHz
133 KHz
Bus Rate w/
4MHz XTAL
200 KHz
167 KHz
143 KHz
125 KHz
111 KHz
100 KHz
91 KHz
84 KHz
77 KHz
72 KHz
67 KHz
CGTCFG — Clock Generator Test Register
Bit 7
6
5
4
TSTSMD BCSS
0
0
RESET:
0
0
0
0
3
2
1
Bit 0
TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
0
0
0
0
Read and write in special mode. Bits 0-3 not writable.
TSTSMD — Test Mode of Slow Mode Divider
0 = Not in Test Mode.
1 = Test slow divider. Internal divider states stored in TSTOUT[3:0]
BCSS— Bus Clock Select Slow
0 = SYSCLK is derived from crystal clock EXTALi.
1 = SYSCLK is derived from Slow clock SLWCLK only in special mode.
When TSTSMD set, TSTOUT[3:0] shows the Slow Mode counter. Bits are not writable.
$00E1
10.6 Clock Divider Chains
Figure 13, Figure 14, Figure 15, and Figure 16 summarize the clock divider chains for the various pe-
ripherals on the MC68HC912BL16.
The “intwai” signal in Figure 13, or wait mode, is the only mechanism for choosing slow clocks versus
normal frequency clocks in normal operating modes.
MC68HC912BL16TS/D
For More Information On This Product,
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