MC68HC912BL16 Datasheet, PDF (55/128 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
Table 17 Interrupt Vector Map
Vector Address
Interrupt Source
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
$FFD6, $FFD7 SCI 0
$FFD4, $FFD5
$FFD2, $FFD3
$FF80–$FFCF
Reserved
ATD
Reserved
CCR
Mask
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Local Enable
Register (Bit)
TMSK1 (C3I)
TMSK1 (C4I)
TMSK1 (C5I)
TMSK1 (C6I)
TMSK1 (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
–
ATDCTL2 (ASCIE)
–
HPRIO Value to
Elevate
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$80–$CE
9.3 Interrupt Control and Priority Registers
INTCR — Interrupt Control Register
$001E
Bit 7
6
5
4
3
2
1
Bit 0
IRQE
IRQEN
DLY
0
0
0
0
0
RESET:
0
1
1
0
0
0
0
0
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin PE1/IRQ).
IRQE can be read anytime and written once in normal modes. In special modes, IRQE can be read any-
time and written anytime, except the first write is ignored.
IRQEN — External IRQ Enable
0 = External IRQ pin disconnected from interrupt logic
1 = External IRQ pin connected to interrupt logic
IRQEN can be read and written anytime in all modes.
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
The delay time of about 4096 cycles is based on the E clock rate.
0 = No stabilization delay imposed on exit from STOP mode. A stable external oscillator must be
supplied.
1 = Stabilization delay is imposed before processing resumes after STOP.
DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and
written anytime.
HPRIO — Highest Priority I Interrupt
$001F
Bit 7
6
5
4
3
2
1
Bit 0
1
1
PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
RESET:
1
1
1
1
0
0
1
0
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
MC68HC912BL16TS/D
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