MC68340FE16E Datasheet, PDF (87/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
S0
S2
S4
CLKOUT
S0
S2
S4
A31–A0
FC3–FC0
R/W
AS
DS
DSACKx
D15–D10
BERR
HALT
WRITE
CYCLE
HALT
WRITE
RERUN
Figure 3-20. Late Retry Sequence
3.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the MC68340 halts external bus
activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not
terminate a bus cycle. Negating and reasserting HALT in accordance with the correct
timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT
affects external bus cycles only, a program that does not require use of the external bus
may continue executing. The single-cycle mode allows the user to proceed through (and
debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a
bus error while HALT is asserted causes a retry operation, the user must anticipate retry
cycles while debugging in the single-cycle mode. The single-step operation and the
software trace capability allow the system debugger to trace single bus cycles, single
instructions, or changes in program flow.
When the MC68340 completes a bus cycle with HALT asserted, D15–D0 is placed in the
high-impedance state, and bus control signals are negated (not high-impedance state);
the A31–A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has
no effect on bus arbitration (see 3.6 Bus Arbitration). When bus arbitration occurs while
the MC68340 is halted, the address and control signals are also placed in the high-
impedance state. Once bus mastership is returned to the MC68340, if HALT is still
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MC68340 USER’S MANUAL
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