MC68340FE16E Datasheet, PDF (273/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
ADDRESS
CH1 CH2
780 7A0
782 7A2
784 7A4
786 7A6
788 7A8
78A 7AA
78C 7AC
78E 7AE
790 7B0
792 7B2
794 7B4
796 7B6
798 7B8
79A 7BA
79C 7BC
79E 7BE
FC
15
8
7
0
S
MODULE CONFIGURATION REGISTER (MCR)
S
RESERVED
S
INTERRUPT REGISTER
S/U
RESERVED
S/U
CHANNEL CONTROL REGISTER
S/U CHANNEL STATUS REGISTER FUNCTION CODE REGISTER
S/U
SOURCE ADDRESS REGISTER MSBs
S/U
SOURCE ADDRESS REGISTER LSBs
S/U
DESTINATION ADDRESS REGISTER MSBs
S/U
DESTINATION ADDRESS REGISTER LSBs
S/U
BYTE TRANSFER COUNTER MSBs
S/U
BYTE TRANSFER COUNTER LSBs
S/U
RESERVED
S/U
RESERVED
S/U
RESERVED
S/U
RESERVED
Figure 6-15. DMA Module Programming Model
In the registers discussed in the following paragraphs, the numbers in the upper right-
hand corner indicate the offset of the register from the base address specified by the
module base address register (MBAR) in the SIM40. The first number is the offset for
channel 1; the second number is the offset for channel 2. The numbers above the register
represent the bit position in the register. The register contains the mnemonic for the bit.
The value of these bits after a hardware reset is shown below the register. The access
privilege is shown in the lower right-hand corner.
NOTE
A CPU32 RESET instruction will not affect the MCR but will
reset all other registers in the DMA module as though a
hardware reset occurred. The term DMA is used to reference
either channel 1 or channel 2, since the two are functionally
equivalent.
6.7.1 Module Configuration Register (MCR)
The MCR controls the DMA channel configuration. Each DMA channel has an MCR. This
register can be either read or written when the channel is enabled and is in the supervisor
state. The MCR is not affected by a CPU32 RESET instruction.
MOTOROLA
MC68340 USER’S MANUAL
6-23
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