MC68340FE16E Datasheet, PDF (334/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
TxCTS—Transmitter Clear-to-Send
1 = Enables clear-to-send operation. The transmitter checks the state of the CTS≈
input each time it is ready to send a character. If CTS≈ is asserted, the character
is transmitted. If CTS≈ is negated, the channel TxDx remains in the high state,
and the transmission is delayed until CTS≈ is asserted. Changes in CTS≈ while
a character is being transmitted do not affect transmission of that character. If
both TxCTS and TxRTS are enabled, TxCTS controls the operation of the
transmitter.
0 = The CTS≈ has no effect on the transmitter.
SB3–SB0—Stop-Bit Length Control
These bits select the length of the stop bit appended to the transmitted character as
listed in Table 7-10. Stop-bit lengths of nine-sixteenth to two bits, in increments of one-
sixteenth bit, are programmable for character lengths of six, seven, and eight bits. For a
character length of five bits, one and one-sixteenth to two bits are programmable in
increments of one-sixteenth bit. In all cases, the receiver only checks for a high
condition at the center of the first stop-bit position—i.e., one bit time after the last data
bit or after the parity bit, if parity is enabled.
If an external 1× clock is used for the transmitter, MR2 bit 3 = 0 selects one stop bit, and
MR2 bit 3 = 1 selects two stop bits for transmission.
Table 7-10. SBx Control Bits
SB3 SB2 SB1 SB0 Length 6-8 Bits
0
0
0
0
0.563
0
0
0
1
0.625
0
0
1
0
0.688
0
0
1
1
0.750
0
1
0
0
0.813
0
1
0
1
0.875
0
1
1
0
0.938
0
1
1
1
1.000
1
0
0
0
1.563
1
0
0
1
1.625
1
0
1
0
1.688
1
0
1
1
1.750
1
1
0
0
1.813
1
1
0
1
1.875
1
1
1
0
1.938
1
1
1
1
2.000
Length 5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
MOTOROLA
MC68340 USER’S MANUAL
7-39
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