MC68340FE16E Datasheet, PDF (68/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
State 4—The MC68340 issues no new control signals during S4.
State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid
during S5 to provide address hold time for memory systems. R/ W, SIZ1/SIZ0, and FC3–
FC0 also remain valid throughout S5. The external device must keep DSACK≈ asserted
until it detects the negation of AS or DS (whichever it detects first). The device must
negate DSACK≈ within approximately one clock period after sensing the negation of AS
or DS. DSACK≈ signals that remain asserted beyond this limit may be prematurely
detected for the next bus cycle.
3.3.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the
arithmetic logic unit, and may write the data out to memory. In the MC68340, this
operation is indivisible, providing semaphore capabilities for multiprocessor systems.
During the entire read-modify-write sequence, the MC68340 asserts RMC to indicate that
an indivisible operation is occurring. The MC68340 does not issue a BG signal in response
to a BR signal during this operation. Figure 3-9 is an example of a functional timing
diagram of a read-modify-write instruction specified in terms of clock periods.
S0
S2
S4
CLK OUT
A31–A30
FC3–FC0
SIZ1–SIZ0
S0
S2
S4
S0
R/W
RMC
AS
DS
DSACKx
D15–D0
READ
INDIVISIBLE
CYCLE
WRITE
Figure 3-9. Read-Modify-Write Cycle Timing
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MC68340 USER’S MANUAL
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