MC68340FE16E Datasheet, PDF (165/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
Instruction
ANDI
EORI
MOVE
MOVEA
MOVEC
MOVES
ORI
RESET
RTE
STOP
LPSTOP
BKPT
BGND
CHK
CHK2
ILLEGAL
TRAP
TRAPcc
TRAPV
ANDI
EORI
MOVE
ORI
Table 5-11. System Control Operations
Operand
Syntax
#〈data〉, SR
#〈data〉, SR
〈ea〉, SR
SR, 〈ea〉
USP, An
An, USP
Rc, Rn
Rn, Rc
Rn, 〈ea〉
〈ea〉, Rn
#〈data〉, SR
none
none
#〈 data〉
#〈 data〉
#〈 data〉
none
〈ea〉, Dn
〈ea〉, Rn
none
#〈 data〉
none
#〈 data〉
none
#〈data〉, CCR
#〈data〉, CCR
〈ea〉, CCR
CCR, 〈ea〉
#〈data〉, CCR
Operand Size
Operation
Privileged
16
Immediate Data Λ SR ⇒ SR
16
Immediate Data ⊕ SR ⇒ SR
16
Source ⇒ SR
16
SR ⇒ Destination
32
USP ⇒ An
32
An ⇒ USP
32
Rc ⇒ Rn
32
Rn ⇒ Rc
8, 16, 32
Rn ⇒ Destination using DFC
Source using SFC ⇒ Rn
16
Immediate Data V SR ⇒ SR
none
Assert RESET line
none
(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒
SP; restore stack according to format
16
Immediate Data ⇒ SR; STOP
none
Immediate Data ⇒ SR; interrupt mask ⇒ EBI;
STOP
Trap Generating
none
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
none
If background mode enabled, then enter background
mode, else format/vector offset ⇒ – (SSP);
PC ⇒ – (SSP); SR ⇒ – (SSP); (vector) ⇒ PC
16, 32
If Dn < 0 or Dn < (ea), then CHK exception
8, 16, 32
If Rn < lower bound or Rn > upper bound, then
CHK exception
none
SSP – 2 ⇒ SSP; vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP);
SSP – 2 ⇒ SSP; SR ⇒ (SSP);
llegal instruction vector address ⇒ PC
none
SSP – 2 ⇒ SSP; format/vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);
vector address ⇒ PC
none
16, 32
If cc true, then TRAP exception
none
If V set, then overflow TRAP exception
Condition Code Register
8
Immediate Data Λ CCR ⇒ CCR
8
Immediate Data ⊕ CCR ⇒ CCR
16
Source ⇒ CCR
16
CCR ⇒ Destination
8
Immediate Data V CCR ⇒ CCR
5-28
MC68340 USER’S MANUAL
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