MC68340FE16E Datasheet, PDF (323/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
MISC3–MISC0—Miscellaneous Commands
These bits select a single command as listed in Table 7-6.
Table 7-6. MISCx Control Bits
MISC3
0
0
0
0
0
0
MISC2
0
0
0
0
1
1
MISC1
0
0
1
1
0
0
MISC0
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Command
No Command
No Command
Reset Receiver
Reset Transmitter
Reset Error Status
Reset Break-Change
Interrupt
Start Break
Stop Break
Assert RTS
Negate RTS
No Command
No Command
No Command
No Command
No Command
No Command
Reset Receiver—The reset receiver command resets the channel receiver. The receiver
is immediately disabled, the FFULL and RxRDY bits in the SR are cleared, and the
receiver FIFO pointer is reinitialized. All other registers are unaltered. This command
should be used in lieu of the receiver disable command whenever the receiver
configuration is changed because it places the receiver in a known state.
Reset Transmitter—The reset transmitter command resets the channel transmitter. The
transmitter is immediately disabled, and the TxEMP and TxRDY bits in the SR are
cleared. All other registers are unaltered. This command should be used in lieu of the
transmitter disable command whenever the transmitter configuration is changed
because it places the transmitter in a known state.
Reset Error Status—The reset error status command clears the channel's RB, FE, PE,
and OE bits (in the SR). This command is also used in the block mode to clear all error
bits after a data block is received.
Reset Break-Change Interrupt—The reset break-change interrupt command clears the
delta break (DBx) bits in the ISR.
7-28
MC68340 USER’S MANUAL
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