MC68340FE16E Datasheet, PDF (292/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
* This code is used to initialize the 68340's internal DMA channel
* registers, providing basic functions for operation.
* The code sets up channel 1 for internal request generation
* to perform a memory block initialization for 100 bytes.
***************************************************************************
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR
EQU $0003FF00 Address of SIM40 Module Base Address Reg.
MODBASE EQU $FFFFF000 SIM40 MBAR address value
***************************************************************************
* DMA Channel 1 equates
DMACH1 EQU $780
Offset from MBAR for channel 1 regs
DMAMCR1 EQU $0
MCR for channel 1
* Channel 1 register offsets from channel 1 base address
DMAINT1 EQU $4
interrupt register channel 1
DMACCR1 EQU $8
control register channel 1
DMACSR1 EQU $A
status register channel 1
DMAFCR1 EQU $B
function code register channel 1
DMASAR1 EQU $C
source address register channel 1
DMADAR1 EQU $10
destination address register channel 1
DMABTC1 EQU $14
byte transfer count register channel 1
SARADD EQU $6000
source address
DARADD EQU $8000
destination address
NUMBYTE EQU $64
number of bytes to transfer
***************************************************************************
***************************************************************************
* Initialize DMA Channel 1
***************************************************************************
LEA MODBASE+DMACH1,A0 Pointer to channel 1
* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make
* sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel
* startup.Supervisor/user reg. unrestricted, MAID field at 3.
* IARB priority at 4.
MOVE.W #$0334,(A0)
* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
CLR.W
DMACCR1(A0)
* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
6-42
MC68340 USER’S MANUAL
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