MC68340FE16E Datasheet, PDF (318/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
ERR—Error Mode
This bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the SR
for the channel.
1 = Block mode—The values in the channel SR are the accumulation (i.e., the logical
OR) of the status for all characters coming to the top of the FIFO since the last
reset error status command for the channel was issued. Refer to 7.4.1.7
Command Register (CR) for more information on serial module commands.
0 = Character mode—The values in the channel SR reflect the status of the
character at the top of the FIFO.
NOTE
ERR = 0 must be used to get the correct A/D flag information
when in multidrop mode.
PM1–PM0—Parity Mode
These bits encode the type of parity used for the channel (see Table 7-2). The parity bit
is added to the transmitted character, and the receiver performs a parity check on
incoming data. These bits can alternatively select multidrop mode for the channel.
PT—Parity Type
This bit selects the parity type if parity is programmed by the parity mode bits, and if
multidrop mode is selected, it configures the transmitter for data character transmission
or address character transmission. Table 7-2 lists the parity mode and type or the
multidrop mode for each combination of the parity mode and the parity type bits.
Table 7-2. PMx and PT Control Bits
PM1
0
0
0
0
1
1
1
PM0
0
0
1
1
0
1
1
Parity Mode
With Parity
With Parity
Force Parity
Force Parity
No Parity
Multidrop Mode
Multidrop Mode
PT
Parity Type
0
Even Parity
1
Odd Parity
0
Low Parity
1
High Parity
X
No Parity
0
Data Character
1
Address Character
B/C1–B/C0—Bits per Character
These bits select the number of data bits per character to be transmitted. The character
length listed in Table 7-3 does not include start, parity, or stop bits.
MOTOROLA
MC68340 USER’S MANUAL
7-23
For More Information On This Product,
Go to: www.freescale.com