MC68340FE16E Datasheet, PDF (36/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
2.1 SIGNAL INDEX
The input and output signals for the MC68340 are listed in Table 2-1. The name,
mnemonic, and brief functional description are presented. For more detail on each signal,
refer to the signal paragraph. Guaranteed timing specifications for the signals listed in
Table 2-1 can be found in Section 11 Electrical Characteristics.
Table 2-1. Signal Index
Signal Name
Address Bus
Address Bus/Port A7–A0/
Interrupt Acknowledge
Data Bus
Function Codes
Chip Select 3–1/
Interrupt Request Level/
Port B4, B2, B1
Chip Select 0/Autovector
Bus Request
Bus Grant
Bus Grant Acknowledge
Data and Size
Acknowledge
Read-Modify-Write Cycle
Address Strobe
Data Strobe
Size
Read/Write
Interrupt Request Level/
Port B7, B6, B5, B3
Reset
Halt
Bus Error
System Clock
Crystal Oscillator
External Filter Capacitor
Mnemonic
A23–A0
A31–A24
D15–D0
FC3–FC0
CS3–CS1
Function
Lower 24 bits of the address bus
Upper eight bits of the address bus, parallel I/O port, or
interrupt acknowledge lines
The 16-bit data bus used to transfer byte or word data
Identify the processor state and the address space of the
current bus cycle
Enables peripherals at programmed addresses, interrupt
priority level to the CPU32, or parallel I/O port
CS0
BR
BG
BGACK
DSACK1,
DSACK0
RMC
AS
DS
SIZ1, SIZ0
R/ W
IRQ7, IRQ6,
IRQ5, IRQ3
RESET
HALT
BERR
CLKOUT
EXTAL, XTAL
XFC
Enables peripherals at programmed addresses or
requests an automatic vector
Indicates that an external device requires bus mastership
Indicates that current bus cycle is complete and the
MC68340 has relinquished the bus
Indicates that an external device has assumed bus
mastership
Provides asynchronous data transfers and dynamic bus
sizing
Identifies the bus cycle as part of an indivisible read -
modify-write operation
Indicates that a valid address is on the address bus
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write
cycle, DS indicates that valid data is on the data bus.
Indicates the number of bytes remaining to be transferred
for this cycle
Indicates the direction of data transfer on the bus
Provides an interrupt priority level to the CPU32 or
becomes a parallel I/O port
System reset
Suspends external bus activity
Indicates an invalid bus operation is being attempted
System clock out
Connections for an external crystal or oscillator to the
internal oscillator circuit
Connection pin for an external capacitor to filter the circuit
of the phase-locked loop
Input/
Output
Out
Out/I/O/Out
I/O
Out
Out/In/
I/O
Out/In
In
Out
In
In
Out
Out
Out
Out
Out
In/I/O
I/O
I/O
In
Out
In, Out
In
2-2
MC68340 USER’S MANUAL
MOTOROLA
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