MC68340FE16E Datasheet, PDF (205/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered
via a double bus fault immediately out of reset.
CPU32 ACTIVITY
ENTER (BDM)
• ASSERT FREEZE SIGNAL
• WAIT FOR COMMAND
EXECUTE COMMAND
• LOAD: NOT READY/ RESPONSE
• PERFORM COMMAND
• STORE RESULTS
D. EVELOPMENT SYSTEM ACTIVITY
SEND INITIAL COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT OUT 17 BITS
• DISABLE SHIFT CLOCK
READ RESULTS/NEW COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT IN/OUT 17 BITS
• DISABLE SHIFT CLOCK
• READ RESULT REGISTER
IF RESULTS =
YES
"NOT READY"
NO
CONTINUE
Figure 5-21. BDM Command Execution Flowchart
5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or
call user code (CALL) command is received. Both GO and CALL flush the instruction
pipeline and prefetch instructions from the location pointed to by the RPC.
The return PC and the memory space referred to by the SR SUPV bit reflect any changes
made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation
of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE and IFETCH
functionality.
5.6.2.7 SERIAL INTERFACE. Communication with the CPU32 during BDM occurs via a
dedicated serial interface, which shares pins with other development features. The BKPT
signal becomes the DSCLK; DSI is received on IFETCH, and DSO is transmitted on
IPIPE.
5-68
MC68340 USER’S MANUAL
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