MC68340FE16E Datasheet, PDF (406/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
11.6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING (See notes (a), (b),
(c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see numbered notes)
3.3 V
3.3 V or 5.0 V
5.0 V
8.39 MHz
16.78 MHz 25.16 MHz
Num.
Characteristic
System Frequency1
Symbol Min Max Min Max Min Max Unit
fsys
dc 8.39 dc 16.78 dc 25.16 MHz
Crystal Frequency
fXTAL 25
50
25
50
25
50 kHz
On-Chip VCO System Frequency
fsys 0.13 8.39 0.13 16.78 0.13 25.16 MHz
On-Chip VCO Frequency Range
fVCO 0.1 16.78 0.1 33.5 0.1 50.3 MHz
External Clock Operation
PLL Start-up Time2
Limp Mode Clock Frequency ³
SYNCR X-bit = 0
SYNCR X-bit = 1
CLKOUT stability ⁴
fsys
trc
flimp
∆_CLK
0
8
0
16
0
25 MHz
— 20 — 20 — 20 ms
kHz
— fsys /2 — fsys /2 — fsys /2
— fsys — fsys — fsys
–1 +1 –1 +1 –1 +1 %
15 ^{CLKOUT Period in Crystal Mode}
tcyc 119.2 — 59.6 —
40
—
ns
1B6 ^{External Clock Input Period}
tEXTcyc 125 — 62.5 —
40
—
ns
1C ^{7 External Clock Input Period with PLL}
tEXTcyc 125 — 62.5 —
40
—
ns
2,3 ^{8 CLKOUT Pulse Width in Crystal Mode}
tCW
56
—
28
—
19
—
ns
2B, 3B9 ^{CLKOUT Pulse Width in External Mode tEXTCW 56}
—
28
—
18
—
ns
2C, ^{CLKOUT Pulse Width in External w/PLL tEXTCW 62.5 —}
31
—
20
—
ns
3C ^{10 Mode}
4,5 ^{CLKOUT Rise and Fall Times}
tCrf
— 10 —
5
—
4
ns
NOTES:
(a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V ±0.3 V are preliminary
and apply only to the appropriate MC68340V low voltage part.
(b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V ±5% operation.
(c) The 25.16 MHz @ 5.0 V ±5% electrical specifications are preliminary.
(d) For extended temperature parts T _A = –40 to +85°C. These specifications are preliminary.
1. All internal registers retain data at 0 Hz.
2. Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 µF is attached to
the XFC pin, and that the crystal oscillator is stable. Lock time is measured from power-up to RESET release.
This specification also applies to the period required for PLL lock after changing the W and Y frequency control
bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock
to lock after LPSTOP.
3. Determined by the initial control voltage applied to the on-chip VCO. The X-bit in the SYNCR controls a divide-
by-two scaler on the system clock output.
4. CLKOUT stability is the average deviation from programmed frequency measured at maximum f _sys .
Measurement is made with a stable external clock input applied using the PLL.
5. All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input.
6. When using the external clock input mode (MODCK reset value = 0 V), the minimum allowable t _EXTcyc period
will be reduced when the duty cycle of the signal applied to EXTAL exceeds 5% tolerance. The relationship
between external clock input duty cycle and minimum tEXTcyc is expressed:
Minimum tEXTcyc period = minimum tEXTCW / (50% – external clock input duty cycle tolerance).
Minimum external clock low and high times are based on a 45% duty cycle.
7. When using the external clock input mode with the PLL (MODCK reset value = 0 V), the external clock input duty
cycle can be at minimum 20% to produce a CLKOUT with a 50% duty cycle.
8. For crystal mode operation, the minimum CLKOUT pulse width is based on a 47% duty cycle.
9. For external clock mode operation, the minimum CLKOUT pulse width is based on a 45% duty cycle, with a 50%
duty cycle input clock.
11-6
MC68340 USER’S MANUAL
MOTOROLA
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