MC68340FE16E Datasheet, PDF (258/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
CLKOUT
CPU CYCLE
S0
S2
S4
A31–A0
DMA READ
S0
S2
S4
DMA READ
S0
S2
S4
CPU CYCLE
S0
FC3–FC0
SIZ1–SIZ0
AS
DS
R/W
D15–D0
DSACKx
DREQx
DONEx
.(...INPUT)
DACKx
DONEx
(OUTPUT)
NOTE:
1. Timing to generate more than one DMA request.
2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for
more than one DMA transfer to be recognized.
Figure 6-5. Single-Address Read Timing (External Burst)
6-8
MC68340 USER’S MANUAL
MOTOROLA
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