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MC68340FE16E Datasheet, PDF (246/441 Pages) Freescale Semiconductor, Inc – Integrated Processor with DMA User’s Manual | |||
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Freescale Semiconductor, Inc.
5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table
indicates the number of clock periods needed for the processor to perform the specified
operation on the given addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
BCHG #, Dn
2
0
6(0/2/0)â
BCHG Dn, Dm
4
0
6(0/1/0)
BCHG #, â©FEAâª
1
2
8(0/2/1)â
BCHG Dn, â©FEA âª
2
2
8(0/1/1)
BCLR #, Dn
2
0
6(0/2/0)â
BCLR Dn, Dm
4
0
6(0/1/0)
BCLR #, â©FEAâª
1
2
8(0/2/1)â
BCLR Dn, â©FEA âª
2
2
8(0/1/1)
BSET #, Dn
2
0
6(0/2/0)â
BSET Dn, Dm
4
0
6(0/1/0)
BSET #, â©FEAâª
1
2
8(0/2/1)â
BSET Dn, â©FEA âª
2
2
8(0/1/1)
BTST #, Dn
2
0
4(0/2/0)â
BTST Dn, Dm
2
0
4(0/1/0)
BTST #, â©FEAâª
1
0
4(0/2/0)â
BTST Dn, â©FEA âª
2
0
8(0/1/0)
â = An # fetch EA time must be added for this instruction: â© FEA ⪠+ â©FEA ⪠+ â©OPER âª
MOTOROLA
MC68340 USERâS MANUAL
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5-109
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