MC68HC705J2 Datasheet, PDF (76/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
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tVDDR
VDD
POR THRESHOLD (TYPICALLY 1–2 V)
OSC1 PIN
INTERNAL
CLOCK1
4064 tcyc
INTERNAL
ADDRESS
BUS1
0FFE2
0FFE2
0FFE2
0FFE2
0FFE2
0FFE2
0FFF3
INTERNAL
DATA
BUS1
NEW
NEW
PCH
PCL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
3. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
Figure 11-8. Power-On Reset Timing
INTERNAL
CLOCK ¹
INTERNAL
ADDRESS
BUS1
INTERNAL
DATA
BUS1
RESET ²
0FFE3
0FFE3
0FFE3
0FFE3
0FFF4 NEW PC NEW PC
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
tRL
NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
3. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
4. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
Figure 11-9. External Reset Timing
11-10
ELECTRICAL SPECIFICATIONS
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Rev. 2