MC68HC705J2 Datasheet, PDF (59/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
10.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
1
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
2
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 10-4 lists these instructions.
3
Table 10-4. Bit Manipulation Instructions
4
Instruction
Mnemonic
5
Clear Bit
BCLR
Branch if Bit Clear
BRCLR
6
Branch if Bit Set
BRSET
7
Set Bit
BSET
8
10.2.5 Control Instructions
9
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 10-5, use inherent addressing.
10
Table 10-5. Control Instructions
11
Instruction
Mnemonic
12
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
13
No Operation
NOP
Reset Stack Pointer
RSP
14
Return from Interrupt
RTI
15
Return from Subroutine
RTS
Set Carry Bit
SEC
16
Set Interrupt Mask
SEI
17
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
18
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
19
Stop CPU Clock and Enable Interrupts
WAIT
20
Rev. 2
INSTRUCTION SET
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10-7