MC68HC705J2 Datasheet, PDF (44/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
7.1 Timer Counter Register (TCR)
1
A 15-stage ripple counter is the core of the timer. The value of the first eight stages
2
is readable at any time from the read-only timer counter register shown in Figure
7-2 .
3
TCR — Timer Counter Register
$0009
4
Bit 7
6
5
4
3
2
1
Bit 0
RESET
0
0
0
0
0
0
0
0
5
Figure 7-2. Timer Counter Register (TCR)
6
Power-on clears the entire counter chain and begins clocking the counter. After
7
4064 cycles of the internal clock, the power-on reset circuit is released, clearing the
counter again and allowing the MCU to come out of reset.
8
A timer overflow function at the eighth counter stage makes timer interrupts
possible every 1024 internal clock cycles.
9
7.2 Timer Control and Status Register (TCSR)
10
Timer interrupt flags, timer interrupt enable bits, and real-time interrupt rate select
11
bits are in the read/write timer control and status register.
12
TCSR — Timer Control and Status Register
$0008
Bit 7
6
5
4
3
2
1
Bit 0
13
TOF
RTIF
TOIE
RTIE
0
RESET
0
0
0
0
0
0
RT1
RT0
0
1
1
14
Figure 7-3. Timer Control and Status Register (TCSR)
15
16
17
18
19
20
TIMER
7-2
Rev. 2
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