MC68HC705J2 Datasheet, PDF (19/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
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SECTION 3
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PARALLEL I/O
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This section describes the two bidirectional I/O ports.
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3.1 I/O Port Function
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The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or an
output. The contents of a port data direction register (DDR) determine the data
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direction for the port. Writing a 1 to a DDR bit enables the output buffer for the
associated port pin; a 0 disables the output buffer. A reset initializes all implemented
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DDR bits to 0, configuring all I/O pins as inputs.
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NOTE
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Connect any unused inputs and I/O pins to an appropriate logical level,
either V_DD or V_SS. Although the I/O ports do not require termination for
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proper operation, termination reduces the possibility of electrostatic
damage.
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A reset does not initialize the two port data registers. The port data registers for ports
A and B are at addresses $0000 and $0001. To avoid undefined levels, write the data ₁₃
registers before writing the data direction registers.
With an I/O port pin programmed as an output, reading the pin actually reads the
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value of the output data latch and not the voltage on the pin itself. When a pin is
programmed as an input, reading the port bit reads the voltage level on the I/O pin. 15
The output data latch can always be written, regardless of the state of its DDR bit.
Refer to Figure 3-1 for typical port circuitry, and to Table 3-1 for a summary of I/O pin ₁₆
functions.
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PARALLEL I/O
Rev. 2
3-1
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