MC68HC705J2 Datasheet, PDF (34/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
The return from interrupt (RTI) instruction causes the CPU to recover the CPU
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registers from the stack as shown in Figure 5-2.
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5.2.1 Timer Interrupts
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The timer generates two kinds of interrupts:
• Timer overflow interrupt
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• Real-time interrupt
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Setting the interrupt mask in the condition code register disables timer interrupts.
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5.2.1.1 Timer Overflow Interrupts
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while
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the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the
timer control and status register. See 7.2 Timer Control and Status Register
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(TCSR).
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5.2.1.2 Real-Time Interrupts
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A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while
the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer
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control and status register. See 7.2 Timer Control and Status Register (TCSR).
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5.2.2 External Interrupt
When a falling edge occurs on the IRQ pin, an external interrupt request is latched.
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When the CPU completes its current instruction, it tests the external interrupt latch.
If the interrupt latch is set and the interrupt mask in the condition code register is
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reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt
latch while it fetches the interrupt vector, so that another external interrupt request
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can be latched during the interrupt service routine. As soon as the interrupt mask
is cleared (usually during the return from interrupt), the CPU can recognize the new
interrupt request.
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Figure 5-3 shows the sequence of events caused by an interrupt.
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RESETS AND INTERRUPTS
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Rev. 2
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