MC68HC705J2 Datasheet, PDF (32/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
A 4064 t_cyc (internal clock cycle) delay after the oscillator becomes active allows
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the clock generator to stabilize. If the RESET pin is at a logical zero at the end of
4064 t_cyc, the MCU remains in the reset condition until the signal on the RESET pin
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goes to a logical one.
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5.1.2 External Reset
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A zero applied to the RESET pin for one and one-half t_cyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
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5.1.3 Computer Operating Properly (COP) Reset
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A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
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timeout period. (See 7.3 COP Timer.) To clear the COP timer and prevent a COP
reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0
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before the COP timer times out. The COP control register is a write-only register
that returns the contents of an EPROM location when read. See Figure 5-1.
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COPR — COP Control Register
$0FF0
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Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
COPR
RESET
—
—
—
—
—
—
—
0
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Figure 5-1. COP Control Register
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COPR — COP Reset
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COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
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5.1.4 Illegal Address Reset
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An opcode fetch from an address that is not in the EPROM (locations
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$0700–$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
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RESETS AND INTERRUPTS
5-2
Rev. 2
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