MC68HC705J2 Datasheet, PDF (45/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
TOF — Timer Overflow Flag
This clearable, read-only bit becomes set when the first eight stages of the counter
roll over from $FF to $00. TOF generates a timer overflow interrupt request if
1
TOFE is also set. Clear TOF by writing a zero to it. Writing a one to TOF has no
effect.
2
RTIF — Real-Time Interrupt Flag
This clearable, read-only bit becomes set when the selected RTI output becomes
3
active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF
by writing a zero to it. Writing a one to RTIF has no effect.
4
TOIE — Timer Overflow Interrupt Enable
5
This read/write bit enables timer overflow interrupts.
1 = Timer overflow interrupts enabled
6
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable
7
This read/write bit enables real-time interrupts
8
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
9
Bits 3 and 2 — Not used. Always read as zeros.
10
RT1, RT0 — Real-Time 1 and 0
These read/write bits select one of four real-time interrupt rates. See Table 7-1. ₁₁
The real-time interrupt rate should be selected by reset initialization software. A
reset sets both RT1 and RT0, selecting the lowest real-time interrupt rate.
12
Changing the real-time interrupt rate near the end of the RTI period or during a
cycle in which the counter is switching can produce unpredictable results.
13
Because the selected RTI output drives the COP timer, changing the real-time
interrupt rate also changes the counting rate of the COP timer.
14
Table 7-1. Real-Time Interrupt Rate Selection
RT1:RT0
00
01
10
11
RTI Rate
f_op ÷ 2¹⁴
f_op ÷ 2¹⁵
f_op ÷ 2¹⁶
f_op ÷ 2¹⁷
RTI Period
(f_op = 2 MHz)
8.2 ms
16.4 ms
32.8 ms
65.5 ms
COP Timeout Period
(-0/+1 RTI Period)
7 × RTI Period
7 × RTI Period
7 × RTI Period
7 × RTI Period
Minimum COP Timeout
Period ( f_op = 2 MHz)
57.3 ms
114.7 ms
229.4 ms
458.8 ms
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16
17
18
19
20
TIMER
Rev. 2
7-3
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