MC68HC705J2 Datasheet, PDF (20/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
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DATA DIRECTION
REGISTER
BIT
LATCHED
OUTPUT DATA
BIT
[1]
I/O
PIN
[3]
[2]
[1] Output buffer enables latched output to drive I/O pin when DDR bit is 1 (output mode).
[2] Input buffer enabled when DDR bit is 0 (input mode).
[3] Input buffer enabled when DDR bit is 1 (output mode).
Figure 3-1. Parallel I/O Port Circuit
Table 3-1. I/O Pin Functions
R/W
DDR Bit
I/O Pin Function
0
0
The I/O pin is an input. Data is written into the output data latch.
0
1
Data is written into the output data latch, which drives the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is an output. The output data latch is read.
NOTE: R/W is an internal MCU signal.
PARALLEL I/O
3-2
Rev. 2
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