MC68HC705J2 Datasheet, PDF (50/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
8.3 Mask Option Register (MOR)
1
The mask option register is an EPROM byte that contains three bits to control the
2
following options:
• MC68HC05J1 emulation mode
3
• External interrupt trigger sensitivity
• COP timer (enable/disable)
4
The mask option register is programmable only when using the bootloader function
5
to download to the EPROM.
6
MOR — Mask Option Register
$0F00
MC68HC05J1 Emulation Mode: $0700
7
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
J1
IRQ
COP
8
Figure 8-2. Mask Option Register (MOR)
9
J1 — MC68HC05J1 Emulation Mode Select
This bit can be read at any time, but can be programmed only by the bootloader.
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1 = Emulation mode selected; MCU functions as MC68HC05J1
0 = (Erased state) MC68HC705J2 native mode selected
11
IRQ — Interrupt Request
12
This bit can be read at any time, but can be programmed only by the bootloader.
1 = IRQ trigger is both edge-sensitive and level-sensitive
13
0 = (Erased state) IRQ trigger is edge-sensitive only
COP — COP Timer Enable
14
This bit can be read at any time, but can be programmed only by the bootloader.
15
1 = COP timer enabled
0 = (Erased state) COP timer disabled
16
NOTE
17
To avoid unintentionally enabling any of the options in the MOR, the
18
user should ensure that location $0F00 of the 8K external EPROM
(2764) is programmed with either the appropriate value for the
options to be enabled or $00. This is necessary because the erased
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state of an 8K external EPROM is $FF, whereas the erased state of
the MOR is $00.
20
BOOTLOADER MODE
8-4
Rev. 2
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