MC68HC705J2 Datasheet, PDF (53/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
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SECTION 10
INSTRUCTION SET
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This section describes the M68HC705J1A addressing modes and instruction
types.
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10.1 Addressing Modes
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The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
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execute an instruction. The eight addressing modes are the following:
• Inherent
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• Immediate
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• Direct
• Extended
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• Indexed, no offset
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• Indexed, 8-bit offset
• Indexed, 16-bit offset
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• Relative
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10.1.1 Inherent
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Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
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registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent
instructions require no memory address and are one byte long.
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10.1.2 Immediate
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Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
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no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
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Rev. 2
INSTRUCTION SET
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