MC68HC705J2 Datasheet, PDF (36/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
Either an edge-sensitive or an edge- and level-sensitive external interrupt trigger
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is programmable in the mask option register. Figure 5-4 shows the internal logic
of this programmable option.
2
3
LEVEL SENSITIVE TRIGGER
4
(MOR OPTION)
VDD
INTERRUPT MASK
EXTERNAL
5
DQ
INTERRUPT
REQUEST
6
IRQ
7
8
CQ
R
RESET
EXTERNAL INTERRUPT
BEING SERVICED
(VECTOR FETCH)
9
Figure 5-4. External Interrupt Trigger Option
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The edge- and level-sensitive trigger option allows multiple external interrupt
sources to be wire-ORed to the IRQ pin. With the level-sensitive trigger option, an
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external interrupt request is latched as long as any source is holding the IRQ pin
low.
12
Setting the interrupt mask in the condition code register disables external
interrupts.
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14
5.2.3 Software Interrupt
The software interrupt (SWI) instruction causes a nonmaskable interrupt.
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RESETS AND INTERRUPTS
5-6
Rev. 2
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