MC68HC705J2 Datasheet, PDF (73/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
11.6 Control Timing (V_DD = 5.0 Vdc)
Table 11-5. Control Timing (V_DD = 5.0 Vdc)
(V_DD = 5.0 Vdc 10%, V_SS = 0 Vdc; T_A = T_L to T_H)
Characteristic
Symbol
Min
Max Unit
Oscillator Frequency
Crystal Option
External Clock Option
f_osc
—
4.2 MHz
dc
4.2
Internal Operating Frequency
Crystal (f_osc ÷ 2)
External Clock (f_osc ÷ 2)
Cycle Time
RESET Pulse Width
Timer Resolution (NOTE 1)
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
Programming Time per Byte
f_op
—
2.1 MHz
dc
2.1
t_cyc
480
—
ns
t_RL
1.5
—
t_cyc
t_RESL
4.0
—
t_cyc
t_ILIH
125
—
ns
t_ILIL
(NOTE 2) —
t_cyc
t_OH, t_OL
90
—
ns
t_EPGM
4
—
ms
NOTES:
1. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
2. The minimum period t_ILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 t_cyc.
IRQ (PIN)
t_ILIH
t_ILIL
Edge-Sensitive Trigger — The minimum tILIH is either 125 ns (VDD = 5 V) or 250 ns (VDD = 3 V). The period tILIL
should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 19 tcyc cycles.
IRQ ₁
t_ILIH
IRQ _n
IRQ (MCU)
NORMALLY
USED WITH
WIRED–OR
CONNECTION
Edge and Level-Sensitive Trigger — If IRQ remains low after interrupt is serviced, the next interrupt is recognized.
Figure 11-6. External Interrupt Timing
Rev. 2
ELECTRICAL SPECIFICATIONS
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