MC68HC705J2 Datasheet, PDF (55/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
10.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
1
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
2
is the conditional address of the operand. The first byte after the opcode is the high
byte of the 16-bit offset; the second byte is the low byte of the offset. These
3
instructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
4
n-element table anywhere in memory.
5
As with direct and extended addressing the Motorola assembler determines the
shortest form of indexed addressing.
6
10.1.8 Relative
7
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
8
following the opcode to the contents of the program counter. If the branch condition
is not true, the CPU goes to the next instruction. The offset is a signed, two’s
9
complement byte that gives a branching range of –128 to +127 bytes from the
address of the next location after the branch instruction.
10
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
11
is within the span of the branch.
12
10.2 Instruction Types
13
The MCU instructions fall into the following five categories:
• Register/Memory Instructions
14
• Read-Modify-Write Instructions
• Jump/Branch Instructions
15
• Bit Manipulation Instructions
16
• Control Instructions
17
18
19
20
Rev. 2
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
10-3