MC68HC705J2 Datasheet, PDF (46/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
7.3 COP Timer
1
Three counter stages at the end of the timer make up the computer operating
2
properly (COP) timer. (See Figure 7-1 .) The COP timer is a software error
detection system that automatically times out and resets the MCU if not cleared
periodically by a program sequence. Writing a zero to bit 0 of the COP register
3
clears the COP timer and prevents a COP timer reset. (See Figure 7-4.)
4
COPR — COP Register
$0FF0
MC68HC05J1 Emulation Mode: $07F0
5
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
COPC
6
RESET
—
—
—
—
—
—
—
0
Figure 7-4. COP Register (COPR)
7
8
COPC — COP Clear
This write-only bit resets the COP timer. Reading address $0FF0 returns the
9
EPROM data at that address.
10
11
12
13
14
15
16
17
18
19
20
TIMER
7-4
Rev. 2
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