MC68HC705J2 Datasheet, PDF (63/82 Pages) Freescale Semiconductor, Inc – member of the low-cost

Freescale Semiconductor, Inc.
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Form
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
Table 10-6. Instruction Set Summary (Continued)
Operation
Description
Effect on
CCR
H I NZC
Increment Byte
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR 3C dd 5
INH 4C
3
— — ¤ ¤ — INH 5C
3
IX1 6C ff 6
IX 7C
5
Unconditional Jump
PC ← Jump Address
DIR BC dd 2
EXT CC hh ll 3
— — — — — IX2 DC ee ff 4
IX1 EC ff 3
IX FC
2
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
—————
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
Load Accumulator
with Memory Byte
A ← (M)
IMM A6 ii 2
DIR B6 dd 3
—— ¤ ¤ —
EXT
IX2
C6 hh ll
D6 ee ff
4
5
IX1 E6 ff 4
IX F6
3
Load Index Register
with Memory Byte
X ← (M)
IMM AE ii 2
DIR BE dd 3
—— ¤ ¤ —
EXT
IX2
CE hh ll
DE ee ff
4
5
IX1 EE ff 4
IX FE
3
Logical Shift Left
(Same as ASL)
C
b7
0
b0
DIR 38 dd 5
INH 48
3
— — ¤ ¤ ¤ INH 58
3
IX1 68 ff 6
IX 78
5
Logical Shift Right
0
b7
C
b0
Unsigned Multiply
Negate Byte
(Two’s Complement)
No Operation
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR 34 dd 5
INH 44
3
— — 0 ¤ ¤ INH 54
3
IX1 64 ff 6
IX 74
5
0 — — — 0 INH 42
11
DIR 30 ii 5
INH 40
3
— — ¤ ¤ ¤ INH 50
3
IX1 60 ff 6
IX 70
5
— — — — — INH 9D
2
Rev. 2
INSTRUCTION SET
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