MC68HC908LJ12 Datasheet, PDF (72/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Configuration Registers (CONFIG)
5.4 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
0
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
SSREC STOP
Reset: 0
0
0
1
0
0
0
= Unimplemented
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 20. Computer Operating Properly (COP).)
1 = COP time out period = 2¹³ – 2⁴ ICLK cycles
0 = COP time out period = 2¹⁸ – 2⁴ ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 21. Low-Voltage
Inhibit (LVI).) Reset sets LVIPWRD.
1 = LVI module power disabled
0 = LVI module power enabled
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Configuration Registers (CONFIG)
Technical Data
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