MC68HC908LJ12 Datasheet, PDF (104/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Clock Generator Module (CGM)
Addr.
$0036
$0037
$0038
$0039
$003A
$003B
Register Name
Bit 7
Read:
PLL Control Register
(PTCL)
Write:
Reset:
PLLIE
0
PLL Bandwidth Control ^Read:
Register Write:
(PBWC) _Reset:
AUTO
0
PLL Multiplier Select ^Read:
0
Register High Write:
(PMSH) _Reset:
0
PLL Multiplier Select ^Read:
Register Low Write:
(PMSL) _Reset:
MUL7
0
PLL VCO Range Select ^Read:
Register Write:
(PMRS) _Reset:
VRS7
0
PLL Reference Divider ^Read:
0
Select Register Write:
(PMDS) _Reset:
0
6
PLLF
5
PLLON
0
1
LOCK
ACQ
0
0
0
0
0
0
MUL6 MUL5
1
0
VRS6 VRS5
1
0
0
0
0
0
= Unimplemented
4
BCS
0
0
0
0
0
MUL4
0
VRS4
0
0
0
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
3
2
1
PRE1 PRE0 VPR1
0
0
0
0
0
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
MUL3 MUL2 MUL1
0
0
0
VRS3 VRS2 VRS1
0
0
0
RDS3 RDS2 RDS1
0
0
0
R = Reserved
Figure 8-2. CGM I/O Register Summary
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
105