MC68HC908LJ12 Datasheet, PDF (141/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

System Integration Module (SIM)
9.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
9.6.1 Interrupts
MODULE
INTERRUPT
I-BIT
IAB
IDB
R/W
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-8 shows interrupt entry timing, and
Figure 9-9 shows interrupt recovery timing.
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 9-8. Interrupt Entry Timing
MODULE
INTERRUPT
I-BIT
IAB
IDB
R/W
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
Figure 9-9. Interrupt Recovery Timing
Technical Data
142
System Integration Module (SIM)
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor