MC68HC908LJ12 Datasheet, PDF (116/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Clock Generator Module (CGM)
8.5.6 CGM VCO Clock Output (CGMVCLK)
CGMVCLK is the clock output from the VCO.
8.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be equal to CGMXCLK, CGMXCLK divided by two, or
CGMPCLK divided by two.
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
8.6 CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 8.6.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 8.6.2 PLL Bandwidth Control Register.)
• PLL multiplier select registers (PMSH and PMSL)
(See 8.6.3 PLL Multiplier Select Registers.)
• PLL VCO range select register (PMRS)
(See 8.6.4 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 8.6.5 PLL Reference Divider Select Register.)
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
117