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MC68HC908LJ12 Datasheet, PDF (159/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units
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Table 10-1. Monitor Mode Signal Requirements and Options
IRQ
RST
Address
$FFFE/
$FFFF
PTA2
PTA1 PTA0(1) PTC1
External
Clock(2)
Bus
Frequency
PLL
COP
Baud
Rate
Comment
X
GND
X
X
X
X
X
X
0
X
Disabled
0
No operation until
reset goes high
VTST(3)
VDD
X
or
VTST
0
1
1
0
4.9152
2.4576
OFF Disabled
9600 PTA1 and PTA2
MHz
MHz
voltages only
required if
IRQ = VTST;
PTC1 determines
frequency divider
VTST(3)
VDD
X
or
VTST
0
1
1
1
9.8304
2.4576
OFF Disabled
9600 PTA1 and PTA2
MHz
MHz
voltages only
required if
IRQ = VTST;
PTC1 determines
frequency divider
VDD
VDD
Blank
X
X
1
X
9.8304
2.4576
OFF Disabled
9600 External frequency
"$FFFF"
MHz
MHz
always divided by 4
GND
VDD
Blank
X
X
1
X
32.768
2.4576
ON Disabled
9600 PLL enabled
"$FFFF"
kHz
MHz
(BCS set)
in monitor code
VDD
VTST
Blank
X
X
X
X
X
or
"$FFFF"
GND
—
OFF Enabled
—
Enters user
mode — will
encounter an illegal
address reset
VDD
VDD Not Blank
X
X
X
X
X
or
or
GND
VTST
—
OFF Enabled
—
Enters user mode
Notes:
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
2. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
3. Monitor mode entry by IRQ = VTST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is bypassed.
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