MC68HC908LJ12 Datasheet, PDF (336/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Liquid Crystal Display Driver (LCD)
16.9.2 LCD Clock Register (LCDCLK)
The LCD clock register (LCDCLK):
• Selects the fast charge duty cycle
• Selects LCD driver duty cycle
• Selects LCD waveform base clock
Address:
Read:
Write:
Reset:
$004F
Bit 7
0
0
6
5
FCCTL1 FCCTL0
0
0
= Unimplemented
4
DUTY1
0
3
DUTY0
0
2
LCLK2
0
1
LCLK1
0
Figure 16-17. LCD Clock Register (LCDCLK)
Bit 0
LCLK0
0
FCCTL[1:0] — Fast Charge Duty Cycle Select
These read/write bits select the duty cycle of the fast charge duration.
Reset clears these bits. (See 16.5.4 Fast Charge and Low Current)
Table 16-4. Fast Charge Duty Cycle Selection
FCCTL1:FCCTL0
00
01
10
11
Fast Charge Duty Cycle
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/32.
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/64.
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/128.
Not used
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Liquid Crystal Display Driver (LCD)
Technical Data
337