MC68HC908LJ12 Datasheet, PDF (190/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Timer Interface Module (TIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
$0032
Timer 2 Channel 0 ^Read:
Register Low Write:
(T2CH0L) _Reset:
Timer 2 Channel 1 Status ^Read:
$0033
and Control Register Write:
(T2SC1) _Reset:
Bit 7
CH1F
0
0
6
CH1IE
0
5
4
3
2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
$0034
Timer 2 Channel 1 ^Read: _{Bit 15}
14
Register High Write:
(T2CH1H) _Reset:
13
12
11
10
Indeterminate after reset
Timer 2 Channel 1 ^Read: _{Bit 7}
6
$0035
Register Low Write:
(T2CH1L) _Reset:
5
4
3
2
Indeterminate after reset
= Unimplemented
Figure 11-2. TIM I/O Register Summary (Sheet 3 of 3)
1
Bit 0
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
11.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
11.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
191