MC68HC908LJ12 Datasheet, PDF (240/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Infrared Serial Communications Interface Module (IRSCI)
13.7.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
13.7.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 13-9):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
SCI_RxD
START BIT
LSB
SAMPLES
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 13-9. Receiver Data Sampling
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI)
Technical Data
241